In an over-sampling type A/D conversion circuit such as a ΔΣ-type A/D conversion circuit, which is a semiconductor integrated circuit, a D/A conversion circuit is used to feedback an output. In a tri-level D/A conversion circuit used for this purpose, output potentials VREF−, VCM and VREF+ are set to be 0V, 1.5V and 3.0V, respectively. A MOS transistor is provided at each output part, which outputs a potential to an output terminal through the MOS transistor upon receiving a corresponding control signal.
In a case that this configuration is manufactured in a manufacturing process for a low voltage device, the potential of VCM, which is an output potential, is close to a threshold value including a substrate bias effect of the MOS transistor, when the VCM is outputted as an intermediate potential of the above-described configuration. For this reason, an on-resistance increases. In a case that a MOS transistor of a low threshold voltage is used to avoid the high on-resistance, an off-resistance of the MOS transistor decreases and generates a leak current when a potential of a DAC capacitance at turn-off time becomes close to a potential of a power supply or ground.
For solving the above-described problems, the following patent documents 1, 2 and non-patent document 1 propose counter-measure technologies. However those documents also have other problems.
For example, in patent document 1, a MOS transistor having a normal threshold voltage is used and a potential of a back gate is set to be equal to an input voltage at turn-on time to thereby decrease an on-resistance. According to this configuration, for controlling the back gate, an impedance of a substrate potential increases resulting in less tolerance to noise. Since each MOS transistor need be separated by a well or the like, a circuit area increases.
In patent document 2 and non-patent document 1, for widening an Input and output ranges, a CMOS switch having a normal threshold voltage and a series circuit of n-type and p-type MOS transistors having low threshold voltages are connected in parallel. However, an Intermediate node in the series circuit of the MOS transistors is likely to become floated at turn-off time and generate errors at high speed operation time. Further, in a case of application to a tri-level D/A conversion circuit, a circuit area increases because a MOS transistor need be provided unnecessarily for one level.    [Patent document 1] JP S59-28723 A    [Patent document 2]U.S. Pat. No. 6,359,496    [Non-patent document 1]S. S. Bazarjani and W. M. Snelgrove, “Low Voltage SC Circuit Design with Low Vt MOS-FETs,” Proc. Of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1021-1024, May 1995